DDR4 borrows from LRDIMM use of load reduction

A combination of lower voltages and higher speeds

DDR3 memory already has trouble achieving the faster speeds at high memory loading.

As you add memory modules on a memory channel (go from 1 DPC to 2 DPC to 3 DPC), the max achievable speeds go down.

At lower voltage (1.35V), the max achievable speeds go down further:

https://ddr3memory.wordpress.com/2012/06/01/impact-of-lowered-voltages-in-ddr4/
Impact of lowered voltages in DDR4
June 1, 2012

DDR4 is expected to run at an even lower voltage (1.2V).

And expected to run at higher frequencies – moving from the 1333MHz or 1600MHz in use now, to 2400MHz or higher speeds.

Load reduction and rank multiplication will be required at not just 3 DPC, but 2 DPC and 1 DPC.

DDR4 borrows from LRDIMMs

Since LRDIMMs are already doing this (copying Netlist IP in load reduction and rank multiplication), DDR4 hopes to use the same techniques as well:

https://ddr3memory.wordpress.com/2012/06/07/jedec-fiddles-with-ddr4-while-lrdimm-burns/
JEDEC fiddles with DDR4 while LRDIMM burns
June 7, 2012

DDR4 has dumped some of the asymmetrical lines and centralized buffer chipset choices in the LRDIMMs (which are the cause of high latency issues in LRDIMMs), in favor of an even closer following of the symmetrical lines and decentralized buffer chipset on the Netlist HyperCloud (see other articles here).

Therefore, at DDR4, the use of load reduction and rank multiplication will become “mainstream” i.e. used at nearly all types of memory loading (3 DPC, 2 DPC and 1 DPC).

http://eda360insider.wordpress.com/2011/05/12/the-ddr4-sdram-spec-and-soc-design-what-do-we-know-now/
The DDR4 SDRAM spec and SoC design. What do we know now?
Posted on May 12, 2011

In addition, most memory experts predict that designs with multiple DDR4 DIMMs on each memory channel will not be able to work reliably (or at all) starting with data transfer rate considerably below the 3.2 Gtransfers/sec maximum. Similarly, DIMMs with multiple memory ranks on the board may also fail before the data transfer rate reaches 3.2 Gtransfers/sec.

There are a couple of possible solutions to these DDR4 signal-integrity challenges. The first and simplest solution is to allow only one DIMM slot per DDR4 memory channel and allow only single-rank DDR4 DIMMs. The problem with this solution is that it increases the number of SoC memory channels for a given memory capacity and thus drives up the SoC’s pin count, cost, and board-level real estate.

No one likes any of those consequences. Not at all. So an alternative solution is the use of load-reduced DIMMs (LRDIMMs) as shown in the following figure.

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8 responses to “DDR4 borrows from LRDIMM use of load reduction

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