Tag Archives: load reduction

HyperCloud to own the 32GB market ?

Marketability as a better RDIMM

UPDATE: 07/09/2012 – buyout
UPDATE: 07/09/2012 – strategic value of RDIMM-compatibility and misconceptions debunked
UPDATE: 07/27/2012 – confirmed HCDIMM similar latency as RDIMMs
UPDATE: 07/27/2012 – confirmed LRDIMM latency and throughput weakness

Is Netlist a buyout candidate ?

Is LRDIMM a dead-end product ?

Is it easier to market a better RDIMM that includes all the features of an LRDIMM ?

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Examining patent docs at USPTO II – sloppy appeals

What sloppy appeals at the USPTO look like

UPDATE: 07/08/2012 – quoting from the pdfs

We’ll shed some light on Inphi’s arguments in appeal of USPTO finding in favor of Netlist in the ‘537 and ‘274 patent reexams.

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Why are LRDIMMs single-sourced by Inphi ?

Inphi as a single point of failure

UPDATE: added 06/21/2012: added info on Montage
UPDATE: 07/06/2012 – now a Montage 1333MHz version like Inphi

The top 3 buffer chipset makers are Inphi, IDTI and Texas Instruments.

However Inphi is the only supplier of “iMB” LRDIMM buffer chipsets for Romley.

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Patent trolls at the JEDEC gate ?

How Netlist differs from Rambus

UPDATE: added 06/22/2012: Analyst on Inphi IPO potential

Rambus was guilty of taking information FROM JEDEC to inform it’s patenting activity, and thus “front-running” the JEDEC activities.

Netlist, in contrast, was an inventor of a technology that it revealed to a JEDEC member under NDA (Non-Disclosure Agreement), which was alleged to have been leaked by that JEDEC member (see below).

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DDR4 borrows from LRDIMM use of load reduction

A combination of lower voltages and higher speeds

DDR3 memory already has trouble achieving the faster speeds at high memory loading.

As you add memory modules on a memory channel (go from 1 DPC to 2 DPC to 3 DPC), the max achievable speeds go down.

At lower voltage (1.35V), the max achievable speeds go down further:

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JEDEC fiddles with DDR4 while LRDIMM burns

JEDEC and DDR4 finalization

UPDATE: 06/10/2012: this article was slashdotted today
UPDATE: 07/24/2012: added Netlist on JEDEC BOD

While JEDEC has time before they finalize the DDR4 standard to secure relevant IP, they did not exercise similar concern when they finalized the LRDIMM standard.

LRDIMMs were standardized without securing the relevant IP.

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Market for HCDIMMs HDIMMs

Market for load reduction

UPDATE: added 06/06/2012: info on LRDIMM market

In summary, if you follow the constraints outlined in the other articles here:

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Examining patent docs at USPTO

Patent and reexamination docs

This will be a simple guide to following the progress of patent and patent reexams at the USPTO.

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Memory choices for the IBM System X x3750 M4 servers

IBM improves the memory bus ?

UPDATE: added 06/05/2012 – possible reason for speedup
UPDATE: added 06/19/2012 – draft IBM Redpaper
UPDATE: added 06/22/2012 – IBM feedback on speedup
UPDATE: added 07/04/2012 – “above 384GB requires HyperCloud”
UPDATE: added 07/26/2012 – LRDIMM underperforms HCDIMM even at same speeds

These are 4-socket servers (4 processors) with 12 DIMMs per processor for a total of:

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Impact of lowered voltages in DDR4

Higher memory load reduces achievable bandwidth (memory loading).

Conversely, moving to higher frequencies at the same load also is hard (if you are already operating at the max speed possible).

Similarly, moving to lower voltages exacerbates the problem.

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